In recent years, phase-locked loop circuits (referred to as “PLL circuits” hereinafter) have been often employed as the built-in clock generator means of microprocessors while the operating frequencies thereof have also increased to offer widened ranges in accordance with the application of such microprocessors.
To enable the PLL circuits to operate in wide regions in this way, use of some bias-generation/control means proportional to the operation frequency is inevitable. Several techniques for achieving this have been disclosed until today.
One example is found in JP-A-4-37219, which discloses therein a technique for attaining a stabilized operation by applying a bias control including the steps of detecting a loop filter voltage and then controlling it at Vcc/2 in any events in view of the fact that at a point whereat an operating frequency was moved out of a preset value a loop filter output voltage can also move in PLL circuits. Another example is taught by JP-A-2-230821 or by JP-A-8-139597, which disclose therein a method of making use of a replica circuit having the same delay characteristics as a current-controlled oscillator (CCO) to set up an operating point of such CCO in PLL circuitry, which method is used to perform setting of the CCO's operating point in a way proportional to an input operating frequency to thereby accomplish the intended operability with increased stability.
However, the prior known approaches above are such that circuitry is designed and controlled under a mere assumption that CCO must be linear in its input/output characteristics which are requisite conditions or criteria for enabling a PLL circuit to operate in a wide range. Unfortunately the input/output characteristics of CCOs in high-frequency regions are non-linear characteristics—in this case, a setup point of the center frequency and/or CCO control gain will likewise become nonlinear so that letting it operate in a wide range can result in major parameters of a PLL control system behaving to go out of the optimal design value, which in turn makes impossible or at least greatly difficult to achieve any stable or stabilized operations. Accordingly, the prior art approaches are encountered with a problem that in order to provide stabilized operability, the CCO must be designed to operate only within a limited low frequency side with good linearity.
While currently available PLL circuits are typically for use in controlling an oscillator in accordance with a phase difference between an input signal and an oscillation signal of the oscillator, achievement of this control requires that a difference in frequency between the input signal and oscillation signal stay within a specified range; otherwise, the PLL circuit will no longer offer its intended functions. In short, prior art PLL circuits suffer from the limited applicability—namely, these may offer expected operability only within a narrow range of a limited frequency difference between the input and oscillation signals.
On the other hand, as the LSI technologies in this field are becoming more advanced every year in per-chip component miniaturization and voltage reduction plus frequency increase, the saturation of CCO characteristics and other nonlinearities are likewise increasing year by year, which in turn makes it extremely difficult to meet the system designer's needs for enhancing operabilities of PLL circuits covering extended ranges.
It should also be noted that prior art circuitry that requires high-speed analog switches, including but not limited to PLL circuits and analog-to-digital (A/D) converter circuits as well as digital-to-analog (D/A) converter circuits or else, is designed to employ a cascode switch circuit and/or a current switch circuit having a level-shift driver stage of low impedance. One exemplary configuration of the current switch circuit with such level-shift drive stage has been set forth in J. Grame, “Monolithic D/A Improves Conversion Time,” EDN Magazine, Mar. 15, 1971 at pp. 39–41.
Incidentally the cascode switch circuit above is incapable of sufficiently shortening the turn-on/off time period because of its time constant occurring due to a parasitic capacitance in switch-off events. This makes it impossible to sufficiently speed up the switching operations.
A problem associated with the current switch circuit with the level-shift drive stage is that this circuit is complicated in configuration of such level-shift drive stage (an increase in number of series-connected components therein) and thus can easily be influenced by unevenness of components. Due to this, the level-shift drive stage must be constituted from an emitter-follower thereby letting this drive stage perform high-voltage operations. Accordingly the current switch circuit with level-shift drive stage is not suitable for use in achieving voltage reduction of LSIs. If an attempt is made to force it to operate at low voltages, then the resulting drive impedance in a direction in which an emitter current decreases relative to a switching signal would become higher than the drive impedance in the opposite direction in which such current increases, thereby causing resultant switching time to increase nonsymmetrically. For this reason, it remains impossible to achieve the intended switching operations at high speeds.